Simulation Based Architectural Power Estimation for PLA - Based

We present an architectural power simulation technique for PLA-based controllers. The contributions of this work are (1) a simple but eecient power characterization of PLAs; and (2) a strategy for developing a simulatable power model from the input description. Node Switching Capacitance (nsc) of a sub-component (such as and plane) in a PLA is the average capacitance switched by a node in the sub-component, when the node undergoes a power consuming transition (0 ! 1). Power characterization involves extracting nsc equations for diierent sub-components as a function of input size, output size and number of terms. Prototype plas whose are employed to derive nsc equations for a given technology. The input description is modiied for power simulation by adding nsc equations with dependent variables instanced to the controller's parameters. For a given input sequence, the modiied vhdl description is simulated to estimate the total power consumption. Experimental Results are obtained with average estimation error of 10.48 % with a minimum error of 0.19% and maximum error of 21.90%.